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hd44102 (dot matrix liquid crystal graphic display column driver) description the hd44102 is a column (segment) driver for dot matrix liquid crystal graphic display systems, storing the display data transferred from a 4-bit or 8-bit microcomputer in the internal display ram and generating dot matrix liquid crystal driving signals. each bit data of display ram corresponds to on/off state of each dot of a liquid crystal display to provide more flexible than character display. the hd44102 is produced by the cmos process. therefore, the combination of hd44102 with a cmos microcontroller can complete portable battery-driven unit utilizing the liquid crystal displays low power dissipation. the combination of hd44102 with the row (common) driver hd44103 facilitates dot matrix liquid crystal graphic display system configuration. features dot matrix liquid crystal graphic display column driver incorporating display ram interfaces with 4-bit or 8-bit mpu ram data directly displayed by internal display ram ram bit data 1: on ram bit data 0: off display ram capacity: 50 8 4 (1600 bits) internal liquid crystal display driver circuit (segment output): 50 segment signal drivers duty factor (can be controlled by external input waveform) selectable duty factors: 1/8, 1/12, 1/16, 1/24, 1/32 wide range of instruction functions display data read/write, display on/off, set address, set display start page, set up/down, read status low power dissipation power supplies: ? cc = 5v 10% ? ee = 0 to ? v cmos process ordering information type no. package HD44102CH 80-pin plastic qfp (fp-80) hd44102d chip
pin arrangement 670 hd44102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gnd m nc 2 1 cl frm db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 d/i r/w e cs 3 cs 2 cs 1 rst bs v cc y 40 y 41 y 42 y 43 y 44 y 45 y 46 y 47 y 48 y 49 y 50 v 4 v 3 v 2 v 1 v ee y 39 y 38 y 37 y 36 y 35 y 34 y 33 y 32 y 31 y 30 y 29 y 28 y 27 y 26 y 25 y 24 y 23 y 22 y 21 y 20 y 19 y 18 nc y 17 y 16 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 (top view)
block diagram hd44102 671 rst bs e, r/w, d/i cs 1 ?s 3 db 0 ?b 7 interface logic input register output register display data x y up/ down display page busy decoder decoder page data lsb msb page 0 lsb msb page 1 lsb msb page 2 lsb msb page 3 driver circuits (50 circuits) latch (50 circuits) display data ram 50 4 8 bit decoder z m cl frm y 1 y 2 y 40 y 50 v 1 v 2 v 3 v 4 ?1 ?2 v cc gnd v ee on/ off address data
pin description pin pin name number i/o function y1?50 50 o liquid crystal display drive output. relationship among output level, m and display data (d): cs1?s3 3 i chip select cs1 cs2 cs3 state l l l non-selected l l h non-selected l h l non-selected l h h selected read/write enable h l l selected write enable only h l h selected write enable only h h l selected write enable only h h h selected read/write enable e 1 i enable at write (r/w = low) data of db0 to db7 is latched at the fall of e. at read (r/w = high) data appears at db0 to db7 while e is at high level. r/w 1 1 read/write r/w = high data appears at db0 to db7 and can be read by the cpu when e = high and cs2, cs3 = high. r/w = low db0 to db7 can accept input when cs2, cs3 = high or cs1 = high. d/i 1 i data/instruction d/i = high indicates that the data of db0 to db7 is display data. d/i = low indicates that the data of db0 to db7 is display control data. m d output level 10 1010 v 1 v 3 v 2 v 4 672 hd44102
pin pin name number i/o function db0?b7 8 i/o data bus, three-state i/o common terminal e r/w cs1 cs2 cs3 state of db0 to db7 hh * h h output state * lh ** input state, * l * hh high impedance others high impedance m 1 i signal to convert liquid crystal display drive output to ac. cl 1 i display synchronous signal at the rise of cl signal, the liquid crystal display drive signal corresponding to display data appears. frm 1 i display synchronous signal (frame signal) this signal presets the 5-bit display line counter and synchronizes a common signal with the frame timing when the frm signal becomes high. ?, ? 2 i 2-phase clock signal for internal operation the ? and ? clocks are used to perform the operations (input/output of display data and execution of instructions) other than display. rst 1 i reset signal the display disappears and y address counter is set in the up counter state by setting the rst signal to low level. after releasing reset, the display off state and up mode is held until the state is changed by the instruction. bs 1 i bus select signal bs = low db0 to db7 operate for 8-bit length. bs = high db4 to db7 are valid for 4-bit length only. 8-bit data is accessed twice in the high and low order. v1, v2, 4 power supply for liquid crystal display drive v3, v4 v1 and v2: selected level v3 and v4: non-selected level v cc 3 power supply gnd v cc ?nd: power supply for internal logic v ee v cc ? ee : power supply for liquid crystal display drive circuit logic hd44102 673
function of each block interface logic the hd44102 can use the data bus in 4-bit or 8-bit word length to enable interface to a 4-bit or 8-bit cpu. 1. 4 bit mode (bs = high) 8-bit data is transferred twice for every 4 bits through the data bus when the bs signal is high. the data bus uses the high order 4 bits (db4 to db7). first, the high order 4 bits (db4 to db7 in 8-bit data length) are transferred and then the low order 4 bits (db0 to db3 in 8-bit data length). 2. 8-bit mode (bs= low) if the bs signal is low, the 8 data bus lines (db0 to db7) are used for data transfer. db7: msb (most significant bit) db0: lsb (least significant bit) for ac timing, refer to note 12 to note 15 of ?lectrical characteristics. 674 hd44102 figure 1 4-bit mode timing busy x 1 x 3 busy d 7 d 3 u/d x 0 x 2 u/d d 6 d 2 off/on y 5 y 1 off/on d 5 d 1 reset y 4 y 0 reset d 4 d 0 busy flag d/i r/w e db 7 db 6 db 5 db 4 busy flag check (status read) address high order write address low order write busy flag check (status read) data high order write data low order write note: execute instructions other than status read in 4-bit length each. the busy flag is set at the fall of the second e signal. the status read is executed once. after the execution of the status read, the first 4 bits are considered the high order 4 bits. therefore, if the busy flag is checked after the transfer of the high order 4 bits, retransfer data from the higher order bits. no busy check is required in the transfer between the high and low order bits.
input register 8-bit data is written into this register by the cpu. the instruction and display data are distinguished by the 8-bit data and d/i signal and then a given operation is performed. data is received at the fall of the e signal when the cs is in the select state and r/w is in write state. output register the output register holds the data read from the display data ram. after display data is read, the display data at the address now indicated is set in this output register. after that, the address is increased or decreased by 1. therefore, when an address is set, the correct data doesnt appear at the read of the first display data. the data at a specified address appears at the second read of data (figure 2). x, y address counter the x, y address counter holds an address for reading/writing display data ram. an address is set in it by the instruction. the y address register is composed of a 50-bit up/down counter. the address is increased or decreased by 1 by the read/write operation of display data. the up/down mode can be determined by the instruction or rst signal. the y address register counts by looping the values of 0 to 49. the x address register has no count function. display on/off flip/flop this flip/flop is set to on/off state by the instruc- tion or rst signal. in the off state, the latch of display data ram output is held reset and the display data output is set to 0. therefore, display disappears. in the on state, the display data appears according to the data in the ram and is displayed. the display data in the ram is independent of the display on/off. up/down flip/flop this flip/flop determines the count mode of the y address counter. in the up mode, the y address register is increased by 1. 0 follows 49. in the down mode, the register is decreased by 1. 0 is followed by 49. hd44102 675 figure 2 data output busy check write address n busy check read data (dummy) busy check read data at address n busy check data read address n ?1 n n ?1 n ?2 data at address n data at address n ?1 d/i r/w e address output register db 0 ?b 7
display page register the display page register holds the 2-bit data that indicates a display start page. this value is preset to the high order 2 bits of the z address counter by the frm signal. this value indicates the value of the display ram page displayed at the top of the screen. busy flag after an instruction other than status read is accepted, the busy flag is set during its effective period, and reset when the instruction is not effective (figure 3). the value can be read out on db7 by the status read instruction. the hd44102 cannot accept any other instructions than the status read in the busy state. make sure the busy flag is reset before issuing an instruction. z address counter the z address counter is a 5-bit counter that counts up at the fall of cl signal and generates an address for outputting the display data synchronized with the common signal. 0 is preset to the low order 3 bits and a display start page to the high order 2 bits by the frm signal. latch the display data from the display data ram is latched at the rise of cl signal. liquid crystal driver circuit each of 50 driver circuits is a multiplex circuit composed of 4 cmos switches. the combination of display data from latches and the m signal causes one of the 4 liquid crystal driver levels, v1, v2, v3 and v4 to be output. 676 hd44102 figure 3 busy flag tbusy e busy 1 f tbusy 3 f f? is ?1, ?2 frequency (half of hd44103 oscillation frequency)
display ram figure 4 relationship between data in ram and display (display start page 0, 1/32 duty) hd44102 677 12345 484950 com1 com2 com3 com4 com5 com6 com7 com8 com9 com30 com31 com32 lsb d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 msb y 0 y 1 y 2 y 3 y 4 y 47 y 48 y 49 x = 0 x = 1 x = 2 x = 3 display pattern driver output y 1 ? 50 data in display ram (y address) 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 (x address)
display control instructions read/write display data sends or receives data to or from the address of the display ram specified in advance. however, a dummy read may be required for reading display data. refer to the description of the output register in function of each block. display on/off set x/y address display start page msb db lsb r/w 0 0 0 0 d/i 0 0 0 0 7 0 0 1 1 6 0 1 0 1 5 1 1 1 1 4 1 1 1 1 3 1 1 1 1 2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 ...... refer to figure 5 (a) ...... refer to figure 5 (b) ...... refer to figure 5 (c) display start page ...... refer to figure 5 (d) msb db lsb r/w 0 0 0 0 d/i 0 0 0 0 7 0 0 1 1 6 0 1 0 1 5 4 3 2 1 0 binary numbers of 0?9 x address (page) y address (address) y address l m l m l m l m 00 01 10 11 page 0 page 1 page 2 page 3 display data ram 48 49 0 1 .... msb db lsb r/w 0 0 d/i 0 0 7 0 0 6 0 0 5 1 1 4 1 1 3 1 1 2 0 0 1 0 0 0 1 0 display on display off turns the display on/off. ram data is not affected. msb db lsb r/w 1 0 d/i 1 1 76543210 (display data) read (cpu ? hd44102) (display data) write (cpu ? hd44102) 678 hd44102
specifies the ram page displayed at the top of the screen. display is as shown in figure 4. when the display duty factor is more than 1/32 (for example, 1/24, 1/16), display begins at a page specified by the display start page only by the number of lines. hd44102 679 figure 5 display start page a b c d (a) start page = page 0 page 0 page 1 page 2 page 3 display data ram a b c d n liquid crystal screen displayed up to here when display duty is 1/n. (n = 8, 12, 16, 24, 32) n a b c d (b) start page = page 1 page 0 page 1 page 2 page 3 display data ram b c d a n liquid crystal screen n a b c d (c) start page = page 2 page 0 page 1 page 2 page 3 display data ram c d a b n liquid crystal screen n a b c d (d) start page = page 3 page 0 page 1 page 2 page 3 display data ram d a b c n liquid crystal screen n
up/down set status read msb db lsb r/w 1 d/i 0 76543210 b u s y u p / d o w n o f f / o n r e b e t 0000 goes to 1 when rst is in the reset state (busy also goes to 1). goes to 0 when rst is in the operating state. goes to 1 in the display off state. goes to 0 on the display on state. goes to 1 when address counter is in the up mode. goes to 0 when address counter is in the down mode. goes to 1 while all other instructions are being executed. while 1, none of the other instructions are accepted. msb db lsb r/w 0 0 d/i 0 0 7 0 0 6 0 0 5 1 1 4 1 1 3 1 1 2 0 0 1 1 1 0 1 0 up mode down mode sets y address register in the up/down counter mode. 680 hd44102
connection between lcd drivers (example of 1/32 duty factor) figure 6 1/32 duty factor connection example hd44102 681 cr rc hd44103 (master) x 1 x 50 shl m/s fs ds 1 ds 2 ds 3 frm m cl dl dr 1 2 open open open open to liquid crystal display v cc gnd dl dr 1 hd44103 (slave) frm m cl x 1 x 12 shl m/s fs ds 1 ds 2 ds 3 cr r c 2 v cc open open to liquid crystal display v cc gnd y 1 y 50 to liquid crystal display hd44102 no. 1 frm m cl 1 2 y 1 y 50 to liquid crystal display hd44102 no. 2 frm m cl 1 2 open
interface to mpu 1. example of connection to hd6800 in the decoder given in this example, the addresses of hd44102 in the address space of hd6800 are: read/write of display data: $'ffff' write of display instruction: $'fffe' read of status: $'fffe' thus, the hd44102 can be controlled by reading/ writing data at these addresses. 682 hd44102 figure 7 example of connection to hd6800 series a 15 to a 1 vma a 0 r/w 2 d 0 to d 7 res hd6800 decoder v cc cs 1 cs 2 cs 3 d/i r/w e db 0 to db 7 rst hd44102 v cc
2. example of connection to hd6801 the hd6801 is set to mode 5. p10?14 are used as output ports, and p30?37 are used as the data bus. the 74ls154 is a 4-to-16 decoder that decodes 4 bits of p10?13 to select the chips. therefore, the hd44102 can be controlled by selecting the chips through p10?13 and speci- fying the d/i signal through p14 in advance, and later conducting memory read or write for external memory space $0100 to $01ff of hd6801. the ios signal is output to sc1, and the r/w signal is output to sc2. for further details on hd6800 and hd6801, refer to their manuals. hd44102 683 figure 8 example of connection to hd6801 a b c d y 0 y 1 y 15 g 1 g 2 74ls154 p 10 p 11 p 12 p 13 (ios) sc1 (r/w) sc2 p 14 e p 30 p 31 p 37 hd6801 (data bus) cs 1 cs 2 cs 3 r/w d/i e pb 0 db 1 db 7 hd44102 no. 1
connection to liquid crystal display figure 9 example of connection to 1/32 duty factor, 1-screen display figure 10 example of connection to 1/16 duty factor, 1-screen display 684 hd44102 hd44103 (master) x 1 x 2 x 20 hd44103 (slave) x 1 x 2 x 12 hd44102 no. 1 y 1 y 50 hd44102 no. 2 y 1 y 50 hd44102 no. 3 y 1 y 50 1 2 20 21 22 32 liquid crystal display panel 32 150 dots hd44103 (master) x 1 x 2 x 16 1 2 15 16 liquid crystal display panel 16 100 dots hd44102 no. 1 y 1 y 50 hd44102 no. 2 y 1 y 50 x 15
figure 11 example of connection to 1/32 duty factor, 2-screen display hd44102 685 hd44103 (master) x 1 x 2 x 20 hd44103 (slave) x 1 x 2 x 12 hd44102 no. 1 y 1 y 50 hd44102 no. 2 y 1 y 50 hd44102 no. 5 y 1 y 40 1 2 liquid crystal display panel 64 240 dots hd44102 no. 6 y 1 y 50 hd44102 no. 7 y 1 y 50 hd44102 no. 10 y 1 y 40 3 20 21 22 32 33 34 35 52 53 54 64 x 3
limitations on using 4-bit interface function the hd44102 usually transfers display control data and display data via 8-bit data bus. it also has the 4-bit interface function in which the hd44102 transfers 8-bit data by dividing it into the high- order 4 bits and the low-order 4-bits in order to reduce the number of wires to be connected. you should take an extra care in using the application with the 4-bit interface function since it has the following limitations. limitations the hd44102 is designed to transfer the high- order 4-bits and the low-order 4-bits of data in that order after busy check. the lsi does not work normally if the signals are in the following state for the time period (indicated with (*) in figure 11) from when the high-order 4 bits are written (or read) to when the low-order 4 bits are written (or read); r/w = high and d/i = low while the chip is being selected (cs1 = high and cs2 = cs3 = dont care, or cs1 = low and cs2 = cs3 = high). if the signals are in the limited state mentioned before for the time period indicated with (*) the lsi does not work normally. please do not make the signals indicated with dotted lines simulta- neously. as far as the time period indicated with (**), there is no problem. the following explains how the malfunction is caused and gives the measures in application. 686 hd44102 figure 12 example of writing display control instructions e cs r/w d/i db 0 ?b 7 busy check writes high-order bits writes low-order bits busy ** * high order bits low order bits
cause busy check checks if the lsi is ready to accept the next instruction or display data by reading the status register to the hd44102. and at the same time, it resets the internal counter counting the order of high-order data and low-order data. this function makes the lsi ready to accept only the high-order data after busy check. strictly speaking, if r/w = high and d/i = low while the chip is being selected, the internal counter is reset and the lsi gets ready to accept high-order bits. therefore, the lsi takes low-order data for high-order data if the state mentioned above exist in the interval between transferring high-order data and trans- ferring low-order data. measures in application 1. hd44102 controlled via port when you control the hd44102 with the port of a single-chip microcomputer, you should take care of the software and observe the limitations strictly. 2. hd44102 controlled via bus a. malfunction caused by hazard hazard of input signals may also cause the phenomenon mentioned before. the phase shift at transition of the input signals may cause the malfunction and so the ac characteristics must be carefully studied. hd44102 687 figure 13 input hazard hazard example writing high-order data e cs r/w
b. using 2-byte instruction in an application with the hd6303, you can prevent malfunction by using 2-byte instructions such as std and stx. this is because the high-order and low-order data are accessed in that order without a break in the last machine cycle of the instruction and r/w and d/i do not change in the meantime. however, you cannot use the least significant bit of the address signals as the d/i signal since the address for the second byte has an added 1. design the cs decoder so that the addresses for the hd44102 should be 2n and 2n + 1, and that those addresses should be accessed when using 2-byte instructions. for example, in figure 15 the address signal a 1 is used as d/i signal and a 2 ? 15 are used for the cs decoder. addresses 4n and 4n+1 are for instruction access and addresses 4n + 2 and 4n + 3 are for display data access. 688 hd44102 figure 14 2-byte instruction figure 15 hd6303 interface 2n 2n+1 high-order data low-order data last 2 machine cycles of 2-byte instruction e cs address (d/i) db 0 ?b 7 cs d/i r/w e hd44102 hd6303 a 2 ? 15 a 1 r/w e decoder
absolute maximum ratings item symbol value unit notes supply voltage (1) v cc ?.3 to +7.0 v 1 supply voltage (2) v ee v cc ?3.5 to v cc + 0.3 v input voltage (1) v t1 ?.3 to v cc + 0.3 v 1, 2 input voltage (2) v t2 v ee ?0.3 to v cc + 0.3 v 3 operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? notes: 1. referenced to gnd = 0. 2. applied to input terminals (except v1, v2, v3, and v4), and i/o common terminals. 3. applied to terminals v1, v2, v3, and v4. hd44102 689
electrical characteristics (v cc = +5 v 10%, gnd = 0 v, v ee = 0 to ? v, ta = ?0 to 75?) (note 4) item symbol min typ max unit test condition note input high voltage (cmos) v ihc 0.7 v cc ? cc v5 input low voltage (cmos) v ilc 0 0.3 v cc v5 input high voltage (ttl) v iht +2.0 v cc v6 input low voltage (ttl) v ilt 0 +0.8 v 6 output high voltage v oh +3.5 v i oh = ?50 a 7 output low voltage v ol +0.4 v i ol = +1.6 ma 7 vi-xj on resistance r on 7.5 k v ee = ? v 10%, load current 100 a input leakage current (1) i il1 ? +1 a v in = v cc to gnd 8 input leakage current (2) i il2 ? +2 a v in = v cc to v ee 9 operating frequency f clk 25 350 khz ?, ? frequency 10 dissipation current (1) i cc1 100 a f clk = 200 khz frame = 11 65 hz during display dissipation current (2) i cc2 500 a access cycle 1 mhz 12 at access notes: 4. specified within this range unless otherwise noted. 5. applied to m, frm, cl, bs, rst, ?, ?. 6. applied to cs1 to cs3, e, d/i, r/w and db0 to db7. 7. applied to db0 to db7. 8. applied to input terminals, m, frm, cl, bs, rst, ?, ?, cs1 to cs3, e, d/i and r/w, and i/o common terminals db0 to db7 at high impedance. 9. applied to v1, v2, v3, and v4. 690 hd44102
10. ? and ? ac characteristics. symbol min typ max unit duty factor duty 20 25 30 % fall time t f 100 ns rise time t r 100 ns phase difference time t l2 0.8 s phase difference time t 21 0.8 s t l + t h 40 s 11. measured by v cc terminal at no output load, at 1/32 duty factor, an frame frequency of 65 hz, in checker pattern display. access from the cpu is stopped. 12. measured by v cc terminal at no output load, 1/32 duty factor and frame frequency of 65 hz. hd44102 691 t l 0.7 v cc 0.5 v cc 0.3 v cc 0.7 v cc 0.5 v cc 0.3 v cc 0.5 v cc t h t l2 t 21 t r t f t r t f t l t h 1 2 f clk = 1 t l + t h d uty = t l t l + t h 100 (%)
interface ac characteristics item symbol min typ max unit notes c cycle time t cyc 1000 ns 13, 14 e high level width p weh 450 ns 13, 14 e low level width p wel 450 ns 13, 14 e rise time t r 25 ns 13, 14 e fall time t f 25 ns 13, 14 address setup time t as 140 ns 13, 14 address hold time t ah 10 ns 13, 14 data setup time t dsw 200 ns 13 data delay time t ddr 320 ns 14, 15 data hold time at write t dhw 10 ns 13 data hold time at read t dhr 20 ns 14 notes: 13. at cpu write 14. at cpu read 692 hd44102 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v t cyc p wel p weh t r t as t as t ah t ah t f 2.0 v 0.8 v t dsw t dhw e r/w cs 1 ?s 3 d/i db 0 ?b 7 t r t cyc p wel p weh t as t as t f t ah t ah 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v t ddr 2.4 v 0.4 v t dhr e r/w cs 1 ?s 3 d/i db 0 ?b 7
15. db0 to db7 load circuits 16. display off at initial power up. the hd44102 can be placed in the display off state by setting terminal rst to low at initial power up. no instruction other than the read status can be accepted while the rst is at the low level. symbol min typ max unit reset time t rst 1.0 s rise time t r 200 ns hd44102 693 r l d 2 d 3 d 4 d 1 r c test point r l r c diodes d 1 to d 4 are all 1s2074 h = 2.4 k w = 11 k w = 130 pf (including jig capacitance) v cc rst t rst t r 0.7 v cc 0.3 v cc 4.5 v

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